One of the properties which inhibits the high frequency and high speed digital operation of bipolar transistors is the capacitive coupling between the base and the emitter and the base and the collector of the bipolar transistor. The capacitive coupling occurs across the depletion regions of the respective junctions. This phenomenon is well known and is explained in Sze, PHYSICS OF SEMICONDUCTOR DEVICES, pp. 79-81(1981). Because the base to emitter junction controls the current flow of the transistor, most transistors are fabricated so that the base to emitter junction has a minimum of interface area. The interface area is that region of the base and emitter which are in contact with each other. Using a simple parallel plate capacitor model, the equation for the capacitance of a junction is EQU C=k60A/d
where,
C is the capacitance of the junction, PA1 k is the dielectric constant of the material between the "plates" of the capacitor, PA1 60 is the permitivity of free space, PA1 A is the area of the "plates", and PA1 d is the width of the junction depletion region.
Thus the capacitance of a junction is directly proportional to the area of the junction and is inversely proportional to the width of the junction depletion region. Thus there are three ways of decreasing the capacitance of a junction: decreasing the dielectric constant of the junction material or a portion of the the junction, decreasing the area of the junction and increasing the thickness of the junction. Because the active junction must consist of the semiconductor material which forms the bipolar transistor, it is usually impractical to change the dielectric constant of the overall junction (active and parasitic) in a bipolar transistor. Therefore, in order to reduce the capacitance of a junction the active junction area must be decreased, the effective junction thickness must be increased and/or the dielectric constant of the parasitic junction regions must be decreased.
FIG. 1 is a side view of a prior art vertical bipolar transistor. Buried collector 3 is formed in substrate 1. An N-type epitaxial layer is formed on substrate 1 and isolation oxide regions 2 are formed in this epitaxial layer. Base region 5 is formed on epitaxial layer 4 and emitter region 6 is formed in base region 5. Contact diffusion 9 allows base contact 8 to make ohmic contact. Emitter contact 7 contacts emitter region 6 directly. In this structure, and in most vertical bipolar transistors, the base to emitter interface area is much less than the base-collector interface area. Therefore by reducing the base to collector capacitance, the overall parasitic capacitance of a vertical bipolar transistor may be minimized. Therefore, it is an object of the present invention to minimize the base to collector capacitance of a vertical bipolar transistor.